30 #define QQQdialect MPLABX 44 #undef QQQMULTIPROCESSEXH 47 #define qqqMaxBranchDepth 20 48 #define QQQstructbitmap 60 #undef QQQTEMPLATEONLY 62 #define QQQUPLOADATEND 64 #undef QQQASHLINGVITRA 66 #define qqqbitmapint unsigned int 68 #undef QQQTIC2XSERIALIO 70 #undef QQQCOMPRESSED_EXH 77 #define UART_71zzopen zzopen 79 #define UART_71zqqzqz1 zqqzqz1 82 #define FILEPOINT FILE * f, 83 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 99 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 100 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 112 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 113 #ifndef LDRA_VOID_FUNC 114 #define LDRA_VOID_FUNC 117 #if defined(QQQMAINFL) 140 #ifdef QQQ_KEEPCOMMENTS 148 #if !defined(QQQSUPPRESS_UNDEF) 154 #undef QQQHITMAP_STORAGE 156 #define qqnull_params void 157 #define QQQ_PROTOTYPE_DEF 159 #undef QQ_ANSI_PROTOTYPE 161 #define QQ_ANSI_PROTOTYPE 1 164 #define QQ_ANSI_PROTOTYPE 1 170 #define ELEMENT(N) qqqbitmapint element##N; 172 #include "UART_71zbelem.def" 176 #define ELEMENT(N) 0, 178 #include "UART_71zbelem.def" 248 #ifndef _SYS_DEFINITIONS_H 249 #define _SYS_DEFINITIONS_H 258 #include "system/common/sys_common.h" 259 #include "system/common/sys_module.h" 343 #ifndef _SYSTEM_CONFIG_H 344 #define _SYSTEM_CONFIG_H 363 #define SYS_VERSION_STR "2.06" 364 #define SYS_VERSION 20600 368 #define SYS_CLK_FREQ 200000000ul 369 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 370 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 371 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 372 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 373 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 374 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 375 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 376 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 377 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 379 #define SYS_PORT_A_ANSEL 0x3F00 380 #define SYS_PORT_A_TRIS 0xFFED 381 #define SYS_PORT_A_LAT 0x0010 382 #define SYS_PORT_A_ODC 0x0000 383 #define SYS_PORT_A_CNPU 0x0020 384 #define SYS_PORT_A_CNPD 0x0000 385 #define SYS_PORT_A_CNEN 0x0021 386 #define SYS_PORT_B_ANSEL 0x10C8 387 #define SYS_PORT_B_TRIS 0x91FF 388 #define SYS_PORT_B_LAT 0x0000 389 #define SYS_PORT_B_ODC 0x0000 390 #define SYS_PORT_B_CNPU 0x0000 391 #define SYS_PORT_B_CNPD 0x0000 392 #define SYS_PORT_B_CNEN 0x0000 393 #define SYS_PORT_C_ANSEL 0xCFE1 394 #define SYS_PORT_C_TRIS 0xFFFF 395 #define SYS_PORT_C_LAT 0x0000 396 #define SYS_PORT_C_ODC 0x0000 397 #define SYS_PORT_C_CNPU 0x0000 398 #define SYS_PORT_C_CNPD 0x0000 399 #define SYS_PORT_C_CNEN 0x0000 400 #define SYS_PORT_D_ANSEL 0xC100 401 #define SYS_PORT_D_TRIS 0xFFFF 402 #define SYS_PORT_D_LAT 0x0000 403 #define SYS_PORT_D_ODC 0x0000 404 #define SYS_PORT_D_CNPU 0x0000 405 #define SYS_PORT_D_CNPD 0x0000 406 #define SYS_PORT_D_CNEN 0x0000 407 #define SYS_PORT_E_ANSEL 0xFC00 408 #define SYS_PORT_E_TRIS 0xFDFF 409 #define SYS_PORT_E_LAT 0x0000 410 #define SYS_PORT_E_ODC 0x0000 411 #define SYS_PORT_E_CNPU 0x0000 412 #define SYS_PORT_E_CNPD 0x0000 413 #define SYS_PORT_E_CNEN 0x0000 414 #define SYS_PORT_F_ANSEL 0xCEC0 415 #define SYS_PORT_F_TRIS 0xEFFF 416 #define SYS_PORT_F_LAT 0x0000 417 #define SYS_PORT_F_ODC 0x0000 418 #define SYS_PORT_F_CNPU 0x0000 419 #define SYS_PORT_F_CNPD 0x0000 420 #define SYS_PORT_F_CNEN 0x0000 421 #define SYS_PORT_G_ANSEL 0x8CBC 422 #define SYS_PORT_G_TRIS 0xDFFF 423 #define SYS_PORT_G_LAT 0x0000 424 #define SYS_PORT_G_ODC 0x0000 425 #define SYS_PORT_G_CNPU 0x0000 426 #define SYS_PORT_G_CNPD 0x0000 427 #define SYS_PORT_G_CNEN 0x0000 428 #define SYS_PORT_H_ANSEL 0x0070 429 #define SYS_PORT_H_TRIS 0xB3FB 430 #define SYS_PORT_H_LAT 0x0000 431 #define SYS_PORT_H_ODC 0x0000 432 #define SYS_PORT_H_CNPU 0x0000 433 #define SYS_PORT_H_CNPD 0x0000 434 #define SYS_PORT_H_CNEN 0x0000 435 #define SYS_PORT_J_ANSEL 0x0000 436 #define SYS_PORT_J_TRIS 0x8B7F 437 #define SYS_PORT_J_LAT 0x0080 438 #define SYS_PORT_J_ODC 0x0000 439 #define SYS_PORT_J_CNPU 0x0000 440 #define SYS_PORT_J_CNPD 0x0000 441 #define SYS_PORT_J_CNEN 0x0800 442 #define SYS_PORT_K_ANSEL 0xFF00 443 #define SYS_PORT_K_TRIS 0xFFFF 444 #define SYS_PORT_K_LAT 0x0000 445 #define SYS_PORT_K_ODC 0x0000 446 #define SYS_PORT_K_CNPU 0x0000 447 #define SYS_PORT_K_CNPD 0x0000 448 #define SYS_PORT_K_CNEN 0x0000 452 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 453 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 454 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 455 #define SYS_TMR_FREQUENCY 1000 456 #define SYS_TMR_FREQUENCY_TOLERANCE 10 457 #define SYS_TMR_UNIT_RESOLUTION 10000 458 #define SYS_TMR_CLIENT_TOLERANCE 10 459 #define SYS_TMR_INTERRUPT_NOTIFICATION false 465 #define DRV_IC_DRIVER_MODE_STATIC 468 #define DRV_SPI_NUMBER_OF_MODULES 6 471 #define DRV_SPI_POLLED 1 472 #define DRV_SPI_ISR 0 473 #define DRV_SPI_MASTER 1 474 #define DRV_SPI_SLAVE 0 476 #define DRV_SPI_EBM 1 477 #define DRV_SPI_8BIT 1 478 #define DRV_SPI_16BIT 1 479 #define DRV_SPI_32BIT 0 480 #define DRV_SPI_DMA 0 482 #define DRV_SPI_INSTANCES_NUMBER 3 483 #define DRV_SPI_CLIENTS_NUMBER 3 484 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 486 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 487 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 488 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 489 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 490 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 491 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 492 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 493 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 494 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 495 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 496 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 497 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 498 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 499 #define DRV_SPI_BAUD_RATE_IDX0 1000000 500 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 501 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 502 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 503 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 504 #define DRV_SPI_QUEUE_SIZE_IDX0 10 505 #define DRV_SPI_RESERVED_JOB_IDX0 1 507 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 508 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 509 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 510 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 511 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 512 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 513 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 514 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 515 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 516 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 517 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 518 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 519 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 520 #define DRV_SPI_BAUD_RATE_IDX1 1000000 521 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 522 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 523 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 524 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 525 #define DRV_SPI_QUEUE_SIZE_IDX1 10 526 #define DRV_SPI_RESERVED_JOB_IDX1 1 528 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 529 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 530 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 531 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 532 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 533 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 534 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 535 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 536 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 537 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 538 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 539 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 540 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 541 #define DRV_SPI_BAUD_RATE_IDX2 500000 542 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 543 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 544 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 545 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 546 #define DRV_SPI_QUEUE_SIZE_IDX2 10 547 #define DRV_SPI_RESERVED_JOB_IDX2 1 549 #define DRV_TMR_INTERRUPT_MODE true 551 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 552 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 553 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 554 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 555 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 556 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 557 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 558 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 559 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 560 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 561 #define DRV_TMR_POWER_STATE_IDX0 562 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 563 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 564 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 565 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 566 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 567 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 568 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 569 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 570 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 571 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 572 #define DRV_TMR_POWER_STATE_IDX1 574 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 575 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 576 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 577 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 578 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 579 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 580 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 581 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 582 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 583 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 584 #define DRV_TMR_POWER_STATE_IDX2 586 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 587 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 588 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 589 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 590 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 591 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 592 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 593 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 594 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 595 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 596 #define DRV_TMR_POWER_STATE_IDX3 598 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 599 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 600 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 601 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 602 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 603 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 604 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 605 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 606 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 607 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 608 #define DRV_TMR_POWER_STATE_IDX4 612 #define DRV_USART_INSTANCES_NUMBER 1 613 #define DRV_USART_CLIENTS_NUMBER 1 614 #define DRV_USART_INTERRUPT_MODE false 615 #define DRV_USART_BYTE_MODEL_SUPPORT true 616 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 617 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 625 #define DRV_USBHS_DEVICE_SUPPORT true 627 #define DRV_USBHS_HOST_SUPPORT false 629 #define DRV_USBHS_INSTANCES_NUMBER 1 631 #define DRV_USBHS_INTERRUPT_MODE true 633 #define DRV_USBHS_ENDPOINTS_NUMBER 2 636 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 638 #define USB_DEVICE_INSTANCES_NUMBER 1 640 #define USB_DEVICE_EP0_BUFFER_SIZE 64 642 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 650 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 651 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 652 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 653 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 654 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 656 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 657 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 658 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 659 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 660 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 662 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 663 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 664 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 665 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 666 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 668 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 669 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 670 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 671 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 672 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 674 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 675 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 676 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 677 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 678 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 680 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 681 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 682 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 683 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 684 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 686 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 687 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 688 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 689 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 690 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 692 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 693 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 694 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 695 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 696 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 698 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 699 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 700 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 701 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 702 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 704 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 705 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 706 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 707 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 708 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 710 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 711 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 712 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 713 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 714 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 716 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 717 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 718 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 719 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 720 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 722 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 723 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 724 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 725 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 726 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 728 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 729 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 730 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 731 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 732 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 734 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 735 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 736 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 737 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 738 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 740 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 741 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 742 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 743 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 744 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 746 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 747 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 748 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 749 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 750 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 752 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 753 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 754 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 755 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 756 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 758 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 759 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 760 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 761 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 762 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 764 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 766 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 768 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 770 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 772 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 774 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 776 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 778 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 780 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 782 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 784 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 786 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 788 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 790 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 792 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 794 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 796 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 797 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 798 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 799 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 800 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 801 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 802 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 851 #ifndef _DRV_COMMON_H 852 #define _DRV_COMMON_H 954 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 964 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 974 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1030 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1041 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1056 #define _PLIB_UNSUPPORTED 1064 #include "system/common/sys_module.h" 1076 #define DRV_IC_INDEX_0 0 1077 #define DRV_IC_INDEX_1 1 1078 #define DRV_IC_INDEX_2 2 1079 #define DRV_IC_INDEX_3 3 1080 #define DRV_IC_INDEX_4 4 1081 #define DRV_IC_INDEX_5 5 1082 #define DRV_IC_INDEX_6 6 1083 #define DRV_IC_INDEX_7 7 1084 #define DRV_IC_INDEX_8 8 1085 #define DRV_IC_INDEX_9 9 1086 #define DRV_IC_INDEX_10 10 1087 #define DRV_IC_INDEX_11 11 1088 #define DRV_IC_INDEX_12 12 1089 #define DRV_IC_INDEX_13 13 1090 #define DRV_IC_INDEX_14 14 1091 #define DRV_IC_INDEX_15 15 1123 const SYS_MODULE_INDEX index ,
1124 const SYS_MODULE_INIT *
const init ) ;
1146 const SYS_MODULE_INDEX drvIndex ,
1191 const SYS_MODULE_INDEX drvIndex ,
1324 #ifndef _DRV_IC_STATIC_H 1325 #define _DRV_IC_STATIC_H 1326 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1327 #define DRV_IC_Close( handle ) 1366 #include "system/devcon/sys_devcon.h" 1367 #include "system/clk/sys_clk.h" 1368 #include "system/int/sys_int.h" 1369 #include "system/tmr/sys_tmr.h" 1411 #ifndef _DRV_ADC_STATIC_H 1412 #define _DRV_ADC_STATIC_H 1413 #include <stdbool.h> 1414 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1415 #include "peripheral/adchs/plib_adchs.h" 1416 #include "peripheral/int/plib_int.h" 1456 uint8_t bufIndex ) ;
1460 uint8_t bufIndex ) ;
1510 #ifndef _DRV_TMR_STATIC_H 1511 #define _DRV_TMR_STATIC_H 1560 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1561 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1562 #include "peripheral/tmr/plib_tmr.h" 1598 #ifndef _TMR_DEFINITIONS_PIC32M_H 1599 #define _TMR_DEFINITIONS_PIC32M_H 1657 #include "system/int/sys_int.h" 1658 #include "system/clk/sys_clk.h" 1677 #define DRV_TMR_INDEX_0 0 1678 #define DRV_TMR_INDEX_1 1 1679 #define DRV_TMR_INDEX_2 2 1680 #define DRV_TMR_INDEX_3 3 1681 #define DRV_TMR_INDEX_4 4 1682 #define DRV_TMR_INDEX_5 5 1683 #define DRV_TMR_INDEX_6 6 1684 #define DRV_TMR_INDEX_7 7 1685 #define DRV_TMR_INDEX_8 8 1686 #define DRV_TMR_INDEX_9 9 1687 #define DRV_TMR_INDEX_10 10 1688 #define DRV_TMR_INDEX_11 11 1699 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1784 uint32_t dividerMin ;
1786 uint32_t dividerMax ;
1789 uint32_t dividerStep ;
1805 SYS_MODULE_INIT moduleInit ;
1807 TMR_MODULE_ID tmrId ;
1811 TMR_PRESCALE prescale ;
1815 INT_SOURCE interruptSource ;
1823 bool asyncWriteEnable ;
1838 uint32_t alarmCount ) ;
1900 const SYS_MODULE_INDEX drvIndex ,
1901 const SYS_MODULE_INIT *
const init ) ;
1941 SYS_MODULE_OBJ
object ) ;
1988 SYS_MODULE_OBJ
object ) ;
2022 SYS_MODULE_OBJ
object ) ;
2076 const SYS_MODULE_INDEX index ,
2177 uint32_t counterPeriod ) ;
2667 TMR_PRESCALE preScale ) ;
2907 #ifndef _DRV_TMR_DEPRECATED_H 2908 #define _DRV_TMR_DEPRECATED_H 2949 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3013 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3078 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3137 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3198 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3257 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3318 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3348 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3380 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3411 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3443 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3505 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3570 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3587 #include "peripheral/tmr/plib_tmr.h" 3588 #include "peripheral/int/plib_int.h" 3590 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3592 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3594 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3596 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3615 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3621 static inline SYS_STATUS
3624 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3635 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3646 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3656 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3665 TMR_PRESCALE prescale ) ;
3696 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3725 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3731 static inline SYS_STATUS
3734 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3745 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3756 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3766 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3775 TMR_PRESCALE prescale ) ;
3806 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3835 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3841 static inline SYS_STATUS
3844 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3855 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3866 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3876 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3885 TMR_PRESCALE prescale ) ;
3916 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3945 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3951 static inline SYS_STATUS
3954 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3965 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3976 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3986 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
3995 TMR_PRESCALE prescale ) ;
4026 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4055 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4061 static inline SYS_STATUS
4064 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4075 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4086 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4096 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4105 TMR_PRESCALE prescale ) ;
4136 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4155 #include "peripheral/int/plib_int.h" 4197 #ifndef _DRV_PMP_STATIC_H 4198 #define _DRV_PMP_STATIC_H 4199 #include "peripheral/pmp/plib_pmp.h" 4214 PMP_DATA_WAIT_STATES dataWait ,
4215 PMP_STROBE_WAIT_STATES strobeWait ,
4216 PMP_DATA_HOLD_STATES dataHold ) ;
4271 #ifndef _DRV_USART_STATIC_H 4272 #define _DRV_USART_STATIC_H 4311 #ifndef _DRV_USART_STATIC_LOCAL_H 4312 #define _DRV_USART_STATIC_LOCAL_H 4319 #include <stdbool.h> 4356 #ifndef _DRV_USART_H 4357 #define _DRV_USART_H 4397 #ifndef _DRV_USART_DEFINITIONS_H 4398 #define _DRV_USART_DEFINITIONS_H 4404 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4405 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4442 #ifndef _PLIB_USART_H 4443 #define _PLIB_USART_H 4486 #ifndef _USART_PROCESSOR_H 4487 #define _USART_PROCESSOR_H 4496 #include <stdbool.h> 4497 #error "No Processor Family specified" 4541 USART_MODULE_ID index ) ;
4571 USART_MODULE_ID index ) ;
4603 USART_MODULE_ID index ) ;
4637 USART_MODULE_ID index ,
4638 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4667 USART_BRG_CLOCK_SOURCE
4669 USART_MODULE_ID index ) ;
4723 USART_MODULE_ID index ) ;
4753 USART_MODULE_ID index ) ;
4782 USART_MODULE_ID index ) ;
4814 USART_MODULE_ID index ) ;
4845 USART_MODULE_ID index ) ;
4887 USART_MODULE_ID index ) ;
4920 USART_MODULE_ID index ) ;
4952 USART_MODULE_ID index ) ;
4993 USART_MODULE_ID index ,
4994 uint32_t clockFrequency ,
4995 uint32_t baudRate ) ;
5036 USART_MODULE_ID index ,
5037 uint32_t clockFrequency ,
5038 uint32_t baudRate ) ;
5071 USART_MODULE_ID index ,
5072 int32_t clockFrequency ) ;
5107 USART_MODULE_ID index ,
5142 USART_MODULE_ID index ) ;
5177 USART_MODULE_ID index ,
5212 USART_MODULE_ID index ) ;
5244 USART_MODULE_ID index ) ;
5278 USART_MODULE_ID index ) ;
5311 USART_MODULE_ID index ) ;
5344 USART_MODULE_ID index ) ;
5378 USART_MODULE_ID index ,
5423 USART_MODULE_ID index ) ;
5457 USART_MODULE_ID index ) ;
5493 USART_MODULE_ID index ) ;
5530 USART_MODULE_ID index ,
5570 USART_MODULE_ID index ) ;
5608 USART_MODULE_ID index ) ;
5643 USART_MODULE_ID index ) ;
5677 USART_MODULE_ID index ) ;
5711 USART_MODULE_ID index ) ;
5744 USART_MODULE_ID index ) ;
5776 USART_MODULE_ID index ) ;
5808 USART_MODULE_ID index ) ;
5841 USART_MODULE_ID index ) ;
5875 USART_MODULE_ID index ) ;
5904 USART_MODULE_ID index ) ;
5933 USART_MODULE_ID index ) ;
5965 USART_MODULE_ID index ) ;
5997 USART_MODULE_ID index ) ;
6027 USART_MODULE_ID index ) ;
6057 USART_MODULE_ID index ) ;
6086 USART_MODULE_ID index ) ;
6115 USART_MODULE_ID index ) ;
6149 USART_MODULE_ID index ,
6150 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6182 USART_MODULE_ID index ,
6183 USART_RECEIVE_INTR_MODE interruptMode ) ;
6216 USART_MODULE_ID index ,
6217 USART_LINECONTROL_MODE dataFlowConfig ) ;
6250 USART_MODULE_ID index ,
6251 USART_HANDSHAKE_MODE handshakeConfig ) ;
6284 USART_MODULE_ID index ,
6315 USART_MODULE_ID index ) ;
6344 USART_MODULE_ID index ) ;
6375 USART_MODULE_ID index ) ;
6406 USART_MODULE_ID index ) ;
6436 USART_MODULE_ID index ) ;
6468 USART_MODULE_ID index ,
6469 USART_OPERATION_MODE operationmode ) ;
6499 USART_MODULE_ID index ) ;
6532 USART_MODULE_ID index ) ;
6561 USART_MODULE_ID index ) ;
6591 USART_MODULE_ID index ) ;
6627 USART_MODULE_ID index ) ;
6678 USART_MODULE_ID index ,
6681 bool wakeFromSleep ,
6726 USART_MODULE_ID index ,
6727 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6728 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6729 USART_OPERATION_MODE operationMode ) ;
6775 USART_MODULE_ID index ,
6776 uint32_t systemClock ,
6822 USART_MODULE_ID index ) ;
6843 USART_MODULE_ID index ) ;
6864 USART_MODULE_ID index ) ;
6898 USART_MODULE_ID index ) ;
6925 USART_MODULE_ID index ) ;
6951 USART_MODULE_ID index ) ;
6978 USART_MODULE_ID index ) ;
7004 USART_MODULE_ID index ) ;
7029 USART_MODULE_ID index ) ;
7055 USART_MODULE_ID index ) ;
7080 USART_MODULE_ID index ) ;
7106 USART_MODULE_ID index ) ;
7131 USART_MODULE_ID index ) ;
7157 USART_MODULE_ID index ) ;
7184 USART_MODULE_ID index ) ;
7210 USART_MODULE_ID index ) ;
7236 USART_MODULE_ID index ) ;
7263 USART_MODULE_ID index ) ;
7290 USART_MODULE_ID index ) ;
7317 USART_MODULE_ID index ) ;
7343 USART_MODULE_ID index ) ;
7368 USART_MODULE_ID index ) ;
7394 USART_MODULE_ID index ) ;
7421 USART_MODULE_ID index ) ;
7447 USART_MODULE_ID index ) ;
7473 USART_MODULE_ID index ) ;
7498 USART_MODULE_ID index ) ;
7523 USART_MODULE_ID index ) ;
7548 USART_MODULE_ID index ) ;
7574 USART_MODULE_ID index ) ;
7599 USART_MODULE_ID index ) ;
7625 USART_MODULE_ID index ) ;
7651 USART_MODULE_ID index ) ;
7676 USART_MODULE_ID index ) ;
7702 USART_MODULE_ID index ) ;
7727 USART_MODULE_ID index ) ;
7752 USART_MODULE_ID index ) ;
7779 USART_MODULE_ID index ) ;
7804 USART_MODULE_ID index ) ;
7830 USART_MODULE_ID index ) ;
7895 #include "system/common/sys_common.h" 7896 #include "system/common/sys_module.h" 7908 #include "system/int/sys_int.h" 7980 #ifndef _SYS_DMA_DEFINITIONS_H 7981 #define _SYS_DMA_DEFINITIONS_H 7987 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7988 #include "system/common/sys_common.h" 7989 #include "system/common/sys_module.h" 8059 #ifndef _PLIB_DMA_PROCESSOR_H 8060 #define _PLIB_DMA_PROCESSOR_H 8061 #error "Can't find header" 8105 DMA_MODULE_ID index ,
8106 DMA_CHANNEL channel ) ;
8140 DMA_MODULE_ID index ,
8141 DMA_CHANNEL channel ,
8142 DMA_CHANNEL_COLLISION collisonType ) ;
8174 DMA_MODULE_ID index ,
8175 DMA_CHANNEL channel ) ;
8207 DMA_MODULE_ID index ,
8208 DMA_CHANNEL channel ) ;
8246 DMA_MODULE_ID index ,
8247 DMA_CHANNEL channel ,
8248 DMA_CHANNEL_PRIORITY channelPriority ) ;
8277 DMA_CHANNEL_PRIORITY
8279 DMA_MODULE_ID index ,
8280 DMA_CHANNEL channel ) ;
8308 DMA_MODULE_ID index ,
8309 DMA_CHANNEL_PRIORITY channelPriority ) ;
8334 DMA_CHANNEL_PRIORITY
8336 DMA_MODULE_ID index ) ;
8366 DMA_MODULE_ID index ,
8367 DMA_CHANNEL channel ) ;
8398 DMA_MODULE_ID index ,
8399 DMA_CHANNEL channel ) ;
8428 DMA_MODULE_ID index ,
8429 DMA_CHANNEL channel ) ;
8458 DMA_MODULE_ID index ,
8459 DMA_CHANNEL channel ) ;
8490 DMA_MODULE_ID index ,
8491 DMA_CHANNEL channel ) ;
8520 DMA_MODULE_ID index ,
8521 DMA_CHANNEL channel ) ;
8552 DMA_MODULE_ID index ,
8553 DMA_CHANNEL channel ) ;
8584 DMA_MODULE_ID index ,
8585 DMA_CHANNEL channel ) ;
8614 DMA_MODULE_ID index ,
8615 DMA_CHANNEL channel ) ;
8646 DMA_MODULE_ID index ,
8647 DMA_CHANNEL channel ) ;
8676 DMA_MODULE_ID index ,
8677 DMA_CHANNEL channel ) ;
8707 DMA_MODULE_ID index ,
8708 DMA_CHANNEL channel ) ;
8738 DMA_MODULE_ID index ,
8739 DMA_CHANNEL channel ) ;
8769 DMA_MODULE_ID index ,
8770 DMA_CHANNEL channel ) ;
8800 DMA_MODULE_ID index ,
8801 DMA_CHANNEL channel ) ;
8832 DMA_MODULE_ID index ,
8833 DMA_CHANNEL channel ) ;
8864 DMA_MODULE_ID index ,
8865 DMA_CHANNEL channel ,
8866 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8895 DMA_CHANNEL_TRANSFER_DIRECTION
8897 DMA_MODULE_ID index ,
8898 DMA_CHANNEL channel ) ;
8934 DMA_MODULE_ID index ,
8935 DMA_CHANNEL channel ,
8937 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8970 DMA_MODULE_ID index ,
8971 DMA_CHANNEL channel ,
8972 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9003 DMA_MODULE_ID index ,
9004 DMA_CHANNEL channel ,
9005 uint16_t peripheraladdress ) ;
9033 DMA_MODULE_ID index ,
9034 DMA_CHANNEL channel ) ;
9065 DMA_MODULE_ID index ,
9066 DMA_CHANNEL channel ,
9067 uint16_t transferCount ) ;
9095 DMA_MODULE_ID index ,
9096 DMA_CHANNEL channel ) ;
9129 DMA_MODULE_ID index ,
9130 DMA_CHANNEL channel ,
9131 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9159 DMA_SOURCE_ADDRESSING_MODE
9161 DMA_MODULE_ID index ,
9162 DMA_CHANNEL channel ) ;
9195 DMA_MODULE_ID index ,
9196 DMA_CHANNEL channel ,
9197 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9226 DMA_DESTINATION_ADDRESSING_MODE
9228 DMA_MODULE_ID index ,
9229 DMA_CHANNEL channel ) ;
9262 DMA_MODULE_ID index ,
9263 DMA_CHANNEL channel ,
9264 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9292 DMA_CHANNEL_ADDRESSING_MODE
9294 DMA_MODULE_ID index ,
9295 DMA_CHANNEL channel ) ;
9333 DMA_MODULE_ID index ,
9334 DMA_CHANNEL channel ,
9335 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9371 DMA_MODULE_ID index ,
9372 DMA_CHANNEL channel ,
9373 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9408 DMA_MODULE_ID index ,
9409 DMA_CHANNEL channel ,
9410 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9439 DMA_CHANNEL_INT_SOURCE
9441 DMA_MODULE_ID index ,
9442 DMA_CHANNEL channel ) ;
9477 DMA_MODULE_ID index ,
9478 DMA_CHANNEL channel ,
9479 DMA_TRIGGER_SOURCE IRQnum ) ;
9514 DMA_MODULE_ID index ,
9515 DMA_CHANNEL channel ,
9516 DMA_TRIGGER_SOURCE IRQ ) ;
9547 DMA_MODULE_ID index ,
9548 DMA_CHANNEL channel ,
9549 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9576 DMA_CHANNEL_DATA_SIZE
9578 DMA_MODULE_ID index ,
9579 DMA_CHANNEL channel ) ;
9613 DMA_MODULE_ID index ,
9614 DMA_CHANNEL channel ,
9615 DMA_TRANSFER_MODE channeltransferMode ) ;
9647 DMA_MODULE_ID index ,
9648 DMA_CHANNEL channel ) ;
9677 DMA_MODULE_ID index ,
9678 DMA_CHANNEL channel ) ;
9708 DMA_MODULE_ID index ,
9709 DMA_CHANNEL channel ) ;
9738 DMA_MODULE_ID index ,
9739 DMA_CHANNEL channel ) ;
9767 DMA_MODULE_ID index ,
9768 DMA_CHANNEL channel ) ;
9798 DMA_MODULE_ID index ,
9799 DMA_CHANNEL channel ) ;
9826 DMA_MODULE_ID index ,
9827 DMA_CHANNEL channel ) ;
9863 DMA_MODULE_ID index ,
9864 DMA_CHANNEL channel ) ;
9895 DMA_MODULE_ID index ,
9896 DMA_CHANNEL channel ) ;
9929 DMA_MODULE_ID index ) ;
9958 DMA_MODULE_ID index ) ;
9988 DMA_MODULE_ID index ) ;
10017 DMA_MODULE_ID index ) ;
10046 DMA_MODULE_ID index ) ;
10076 DMA_MODULE_ID index ) ;
10104 DMA_MODULE_ID index ) ;
10132 DMA_MODULE_ID index ) ;
10160 DMA_MODULE_ID index ) ;
10189 DMA_MODULE_ID index ) ;
10217 DMA_MODULE_ID index ) ;
10251 DMA_MODULE_ID index ) ;
10281 DMA_MODULE_ID index ) ;
10311 DMA_MODULE_ID index ) ;
10340 DMA_MODULE_ID index ) ;
10375 DMA_MODULE_ID index ,
10376 DMA_CHANNEL channel ) ;
10405 DMA_MODULE_ID index ) ;
10437 DMA_MODULE_ID index ,
10438 DMA_CRC_TYPE CRCType ) ;
10469 DMA_MODULE_ID index ) ;
10499 DMA_MODULE_ID index ) ;
10529 DMA_MODULE_ID index ) ;
10559 DMA_MODULE_ID index ) ;
10588 DMA_MODULE_ID index ) ;
10618 DMA_MODULE_ID index ) ;
10647 DMA_MODULE_ID index ) ;
10677 DMA_MODULE_ID index ,
10678 uint8_t polyLength ) ;
10707 DMA_MODULE_ID index ) ;
10736 DMA_MODULE_ID index ,
10737 DMA_CRC_BIT_ORDER bitOrder ) ;
10768 DMA_MODULE_ID index ) ;
10797 DMA_MODULE_ID index ) ;
10827 DMA_MODULE_ID index ,
10828 DMA_CRC_BYTE_ORDER byteOrder ) ;
10857 DMA_MODULE_ID index ) ;
10888 DMA_MODULE_ID index ) ;
10920 DMA_MODULE_ID index ,
10921 uint32_t DMACRCdata ) ;
10952 DMA_MODULE_ID index ) ;
10985 DMA_MODULE_ID index ,
10986 uint32_t DMACRCXOREnableMask ) ;
11024 DMA_MODULE_ID index ,
11025 DMA_CHANNEL dmaChannel ) ;
11062 DMA_MODULE_ID index ,
11063 DMA_CHANNEL dmaChannel ,
11064 uint32_t sourceStartAddress ) ;
11098 DMA_MODULE_ID index ,
11099 DMA_CHANNEL dmaChannel ) ;
11137 DMA_MODULE_ID index ,
11138 DMA_CHANNEL dmaChannel ,
11139 uint32_t destinationStartAddress ) ;
11179 DMA_MODULE_ID index ,
11180 DMA_CHANNEL dmaChannel ) ;
11219 DMA_MODULE_ID index ,
11220 DMA_CHANNEL dmaChannel ,
11221 uint16_t sourceSize ) ;
11256 DMA_MODULE_ID index ,
11257 DMA_CHANNEL dmaChannel ) ;
11294 DMA_MODULE_ID index ,
11295 DMA_CHANNEL dmaChannel ,
11296 uint16_t destinationSize ) ;
11330 DMA_MODULE_ID index ,
11331 DMA_CHANNEL dmaChannel ) ;
11366 DMA_MODULE_ID index ,
11367 DMA_CHANNEL dmaChannel ) ;
11402 DMA_MODULE_ID index ,
11403 DMA_CHANNEL dmaChannel ) ;
11440 DMA_MODULE_ID index ,
11441 DMA_CHANNEL dmaChannel ,
11442 uint16_t CellSize ) ;
11476 DMA_MODULE_ID index ,
11477 DMA_CHANNEL dmaChannel ) ;
11514 DMA_MODULE_ID index ,
11515 DMA_CHANNEL dmaChannel ) ;
11554 DMA_MODULE_ID index ,
11555 DMA_CHANNEL dmaChannel ,
11556 uint16_t patternData ) ;
11600 DMA_MODULE_ID index ,
11601 DMA_CHANNEL dmaChannel ,
11602 DMA_INT_TYPE dmaINTSource ) ;
11637 DMA_MODULE_ID index ,
11638 DMA_CHANNEL dmaChannel ,
11639 DMA_INT_TYPE dmaINTSource ) ;
11675 DMA_MODULE_ID index ,
11676 DMA_CHANNEL dmaChannel ,
11677 DMA_INT_TYPE dmaINTSource ) ;
11711 DMA_MODULE_ID index ,
11712 DMA_CHANNEL dmaChannel ,
11713 DMA_INT_TYPE dmaINTSource ) ;
11747 DMA_MODULE_ID index ,
11748 DMA_CHANNEL dmaChannel ,
11749 DMA_INT_TYPE dmaINTSource ) ;
11787 DMA_MODULE_ID index ,
11788 DMA_CHANNEL dmaChannel ,
11789 DMA_INT_TYPE dmaINTSource ) ;
11822 DMA_MODULE_ID index ,
11823 DMA_CHANNEL dmaChannel ,
11824 DMA_PATTERN_LENGTH patternLen ) ;
11857 DMA_MODULE_ID index ,
11858 DMA_CHANNEL dmaChannel ) ;
11888 DMA_MODULE_ID index ,
11889 DMA_CHANNEL channel ) ;
11922 DMA_MODULE_ID index ,
11923 DMA_CHANNEL channel ) ;
11953 DMA_MODULE_ID index ,
11954 DMA_CHANNEL channel ) ;
11986 DMA_MODULE_ID index ,
11987 DMA_CHANNEL channel ,
11988 uint8_t pattern ) ;
12019 DMA_MODULE_ID index ,
12020 DMA_CHANNEL channel ) ;
12052 DMA_MODULE_ID index ) ;
12077 DMA_MODULE_ID index ) ;
12101 DMA_MODULE_ID index ) ;
12126 DMA_MODULE_ID index ) ;
12149 DMA_MODULE_ID index ) ;
12173 DMA_MODULE_ID index ) ;
12196 DMA_MODULE_ID index ) ;
12220 DMA_MODULE_ID index ) ;
12244 DMA_MODULE_ID index ) ;
12269 DMA_MODULE_ID index ) ;
12293 DMA_MODULE_ID index ) ;
12317 DMA_MODULE_ID index ) ;
12340 DMA_MODULE_ID index ) ;
12364 DMA_MODULE_ID index ) ;
12388 DMA_MODULE_ID index ) ;
12412 DMA_MODULE_ID index ) ;
12436 DMA_MODULE_ID index ) ;
12460 DMA_MODULE_ID index ) ;
12483 DMA_MODULE_ID index ) ;
12508 DMA_MODULE_ID index ) ;
12533 DMA_MODULE_ID index ) ;
12557 DMA_MODULE_ID index ) ;
12582 DMA_MODULE_ID index ) ;
12606 DMA_MODULE_ID index ) ;
12630 DMA_MODULE_ID index ) ;
12656 DMA_MODULE_ID index ) ;
12681 DMA_MODULE_ID index ) ;
12705 DMA_MODULE_ID index ) ;
12730 DMA_MODULE_ID index ) ;
12753 DMA_MODULE_ID index ) ;
12776 DMA_MODULE_ID index ) ;
12799 DMA_MODULE_ID index ) ;
12822 DMA_MODULE_ID index ) ;
12847 DMA_MODULE_ID index ) ;
12872 DMA_MODULE_ID index ) ;
12896 DMA_MODULE_ID index ) ;
12921 DMA_MODULE_ID index ) ;
12945 DMA_MODULE_ID index ) ;
12969 DMA_MODULE_ID index ) ;
12992 DMA_MODULE_ID index ) ;
13015 DMA_MODULE_ID index ) ;
13039 DMA_MODULE_ID index ) ;
13063 DMA_MODULE_ID index ) ;
13087 DMA_MODULE_ID index ) ;
13114 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13127 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13140 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13170 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13344 DMA_CRC_TYPE type ;
13350 uint8_t polyLength ;
13353 DMA_CRC_BIT_ORDER bitOrder ;
13356 DMA_CRC_BYTE_ORDER byteOrder ;
13366 uint32_t xorBitMask ;
13491 SYS_MODULE_OBJ
object ,
13492 DMA_CHANNEL activeChannel ) ;
13495 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13540 uintptr_t contextHandle ) ;
13586 const SYS_MODULE_INIT *
const init ) ;
13637 DMA_CHANNEL channel ) ;
13723 DMA_TRIGGER_SOURCE eventSrc ) ;
13801 DMA_PATTERN_LENGTH length ,
13803 uint8_t ignorePattern ) ;
14056 const void * srcAddr ,
14058 const void * destAddr ,
14060 size_t cellSize ) ;
14157 const void * srcAddr ,
14159 const void * destAddr ,
14161 size_t cellSize ) ;
14357 const uintptr_t contextHandle ) ;
14653 DMA_TRIGGER_SOURCE eventSrc ) ;
14832 SYS_MODULE_OBJ
object ,
14833 DMA_CHANNEL activeChannel ) ;
14843 SYS_MODULE_OBJ
object ) ;
14853 SYS_MODULE_OBJ
object ,
14854 DMA_CHANNEL activeChannel ) ;
14881 #define DRV_USART_INDEX_0 0 14882 #define DRV_USART_INDEX_1 1 14883 #define DRV_USART_INDEX_2 2 14884 #define DRV_USART_INDEX_3 3 14885 #define DRV_USART_INDEX_4 4 14886 #define DRV_USART_INDEX_5 5 14900 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14911 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14922 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14956 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15107 uintptr_t context ) ;
15155 USART_HANDSHAKE_MODE_FLOW_CONTROL
15159 USART_HANDSHAKE_MODE_SIMPLEX
15321 } AddressedModeInit ;
15346 = USART_ERROR_PARITY
15351 = USART_ERROR_FRAMING
15356 = USART_ERROR_RECEIVER_OVERRUN
15438 SYS_MODULE_INIT moduleInit ;
15442 USART_MODULE_ID usartID ;
15460 uint32_t brgClock ;
15476 USART_OPERATION_MODE linesEnable ;
15480 INT_SOURCE interruptTransmit ;
15484 INT_SOURCE interruptReceive ;
15488 INT_SOURCE interruptError ;
15493 unsigned int queueSizeReceive ;
15498 unsigned int queueSizeTransmit ;
15502 DMA_CHANNEL dmaChannelTransmit ;
15506 DMA_CHANNEL dmaChannelReceive ;
15510 INT_SOURCE dmaInterruptTransmit ;
15514 INT_SOURCE dmaInterruptReceive ;
15598 const SYS_MODULE_INDEX index ,
15599 const SYS_MODULE_INIT *
const init ) ;
15637 SYS_MODULE_OBJ
object ) ;
15675 SYS_MODULE_OBJ
object ) ;
15716 SYS_MODULE_OBJ
object ) ;
15757 SYS_MODULE_OBJ
object ) ;
15798 SYS_MODULE_OBJ
object ) ;
15877 const SYS_MODULE_INDEX index ,
16061 const size_t size ) ;
16254 const size_t size ) ;
16342 const uintptr_t context ) ;
16609 const size_t numbytes ) ;
16677 const size_t numbytes ) ;
16814 const uint8_t byte ) ;
17032 const SYS_MODULE_INDEX index ,
17085 const SYS_MODULE_INDEX index ,
17134 const SYS_MODULE_INDEX index ,
17349 #ifndef _DRV_USART_FEATURE_MAPPING_H 17350 #define _DRV_USART_FEATURE_MAPPING_H 17359 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17360 #define _DRV_USART_InterruptSourceEnable( source ) 17361 #define _DRV_USART_InterruptSourceDisable( source ) false 17362 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17363 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17364 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17365 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17366 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17369 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17378 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17379 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17380 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17381 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17382 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17395 #include "system/clk/sys_clk.h" 17396 #include "system/int/sys_int.h" 17434 #ifndef _SYS_DEBUG_H 17435 #define _SYS_DEBUG_H 17436 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17439 #define SYS_DEBUG_BUFFER_DMA_READY 17489 #define SYS_DEBUG_INDEX_0 0 17505 SYS_MODULE_INIT moduleInit ;
17509 SYS_MODULE_INDEX consoleIndex ;
17557 const SYS_MODULE_INDEX index ,
17558 const SYS_MODULE_INIT *
const init ) ;
17598 SYS_MODULE_OBJ
object ,
17599 const SYS_MODULE_INIT *
const init ) ;
17629 SYS_MODULE_OBJ
object ) ;
17662 SYS_MODULE_OBJ
object ) ;
17706 SYS_MODULE_OBJ
object ) ;
17749 const char * message ) ;
17799 const char * format ,
17889 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17933 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17976 #define SYS_MESSAGE( message ) 18009 #define SYS_DEBUG_MESSAGE( level , message ) 18056 #define SYS_PRINT( fmt ,... ) 18104 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18129 #define SYS_DEBUG_BreakPoint( ) 18138 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18139 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18140 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18157 #define _DRV_USART_RX_DEPTH 9 18223 const SYS_MODULE_INDEX index ,
18248 const uint8_t byte ) ;
18319 #ifndef _SYS_PORTS_H 18320 #define _SYS_PORTS_H 18359 #ifndef _SYS_PORTS_DEFINITIONS_H 18360 #define _SYS_PORTS_DEFINITIONS_H 18366 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18367 #include "system/common/sys_common.h" 18368 #include "system/common/sys_module.h" 18405 #ifndef _PLIB_PORTS_H 18406 #define _PLIB_PORTS_H 18407 #include <stdint.h> 18408 #include <stddef.h> 18473 #ifndef _PLIB_PORTS_PROCESSOR_H 18474 #define _PLIB_PORTS_PROCESSOR_H 18475 #error "Can't find header" 18525 PORTS_MODULE_ID index ,
18526 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18527 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18570 PORTS_MODULE_ID index ,
18571 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18572 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18607 PORTS_MODULE_ID index ,
18608 PORTS_ANALOG_PIN pin ,
18609 PORTS_PIN_MODE mode ) ;
18649 PORTS_MODULE_ID index ,
18650 PORTS_CHANNEL channel ,
18651 PORTS_BIT_POS bitPos ,
18652 PORTS_PIN_MODE mode ) ;
18687 PORTS_MODULE_ID index ,
18688 PORTS_CHANNEL channel ,
18689 PORTS_BIT_POS bitPos ) ;
18723 PORTS_MODULE_ID index ,
18724 PORTS_CHANNEL channel ,
18725 PORTS_BIT_POS bitPos ) ;
18762 PORTS_MODULE_ID index ,
18763 PORTS_CHANNEL channel ,
18764 PORTS_BIT_POS bitPos ) ;
18805 PORTS_MODULE_ID index ,
18806 PORTS_CHANNEL channel ,
18807 PORTS_BIT_POS bitPos ) ;
18846 PORTS_MODULE_ID index ,
18847 PORTS_CHANNEL channel ,
18848 PORTS_BIT_POS bitPos ) ;
18886 PORTS_MODULE_ID index ,
18887 PORTS_CHANNEL channel ,
18888 PORTS_BIT_POS bitPos ) ;
18923 PORTS_MODULE_ID index ,
18924 PORTS_CHANNEL channel ) ;
18959 PORTS_MODULE_ID index ,
18960 PORTS_CHANNEL channel ) ;
18997 PORTS_MODULE_ID index ,
18998 PORTS_CHANNEL channel ) ;
19035 PORTS_MODULE_ID index ,
19036 PORTS_CHANNEL channel ) ;
19073 PORTS_MODULE_ID index ,
19074 PORTS_CHANNEL channel ,
19075 PORTS_BIT_POS bitPos ) ;
19112 PORTS_MODULE_ID index ,
19113 PORTS_CHANNEL channel ,
19114 PORTS_BIT_POS bitPos ) ;
19152 PORTS_MODULE_ID index ,
19153 PORTS_CHANNEL channel ,
19154 PORTS_BIT_POS bitPos ) ;
19191 PORTS_MODULE_ID index ,
19192 PORTS_CHANNEL channel ,
19193 PORTS_BIT_POS bitPos ,
19228 PORTS_MODULE_ID index ,
19229 PORTS_CHANNEL channel ,
19230 PORTS_BIT_POS bitPos ) ;
19264 PORTS_MODULE_ID index ,
19265 PORTS_CHANNEL channel ,
19266 PORTS_BIT_POS bitPos ) ;
19300 PORTS_MODULE_ID index ,
19301 PORTS_CHANNEL channel ,
19302 PORTS_BIT_POS bitPos ) ;
19337 PORTS_MODULE_ID index ,
19338 PORTS_CHANNEL channel ,
19339 PORTS_BIT_POS bitPos ) ;
19374 PORTS_MODULE_ID index ,
19375 PORTS_CHANNEL channel ,
19376 PORTS_BIT_POS bitPos ) ;
19410 PORTS_MODULE_ID index ,
19411 PORTS_CHANNEL channel ,
19412 PORTS_BIT_POS bitPos ) ;
19446 PORTS_MODULE_ID index ,
19447 PORTS_CHANNEL channel ,
19448 PORTS_BIT_POS bitPos ) ;
19486 PORTS_MODULE_ID index ,
19487 PORTS_CHANNEL channel ) ;
19521 PORTS_MODULE_ID index ,
19522 PORTS_CHANNEL channel ) ;
19556 PORTS_MODULE_ID index ,
19557 PORTS_CHANNEL channel ,
19600 PORTS_MODULE_ID index ,
19601 PORTS_CHANNEL channel ,
19637 PORTS_MODULE_ID index ,
19638 PORTS_CHANNEL channel ,
19673 PORTS_MODULE_ID index ,
19674 PORTS_CHANNEL channel ,
19710 PORTS_MODULE_ID index ,
19711 PORTS_CHANNEL channel ,
19746 PORTS_MODULE_ID index ,
19747 PORTS_CHANNEL channel ,
19780 PORTS_MODULE_ID index ,
19781 PORTS_CHANNEL channel ) ;
19815 PORTS_MODULE_ID index ,
19816 PORTS_CHANNEL channel ,
19852 PORTS_MODULE_ID index ,
19853 PORTS_CHANNEL channel ,
19899 PORTS_MODULE_ID index ,
19900 PORTS_CHANNEL channel ,
19902 PORTS_PIN_MODE mode ) ;
19944 PORTS_MODULE_ID index ,
19945 PORTS_CHANNEL channel ,
19988 PORTS_MODULE_ID index ,
19989 PORTS_CHANNEL channel ,
20029 PORTS_MODULE_ID index ,
20030 PORTS_CHANNEL channel ,
20070 PORTS_MODULE_ID index ,
20071 PORTS_CHANNEL channel ,
20115 PORTS_MODULE_ID index ,
20116 PORTS_CHANNEL channel ,
20160 PORTS_MODULE_ID index ,
20161 PORTS_CHANNEL channel ,
20207 PORTS_MODULE_ID index ,
20208 PORTS_AN_PIN anPins ,
20209 PORTS_PIN_MODE mode ) ;
20252 PORTS_MODULE_ID index ,
20253 PORTS_CN_PIN cnPins ) ;
20297 PORTS_MODULE_ID index ,
20298 PORTS_CN_PIN cnPins ) ;
20341 PORTS_MODULE_ID index ,
20342 PORTS_CN_PIN cnPins ) ;
20385 PORTS_MODULE_ID index ,
20386 PORTS_CN_PIN cnPins ) ;
20420 PORTS_MODULE_ID index ) ;
20453 PORTS_MODULE_ID index ) ;
20489 PORTS_MODULE_ID index ,
20490 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20526 PORTS_MODULE_ID index ,
20527 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20564 PORTS_MODULE_ID index ) ;
20598 PORTS_MODULE_ID index ) ;
20634 PORTS_MODULE_ID index ,
20635 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20671 PORTS_MODULE_ID index ,
20672 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20717 PORTS_MODULE_ID index ,
20718 PORTS_CHANNEL channel ,
20720 PORTS_PIN_SLEW_RATE slewRate ) ;
20757 PORTS_PIN_SLEW_RATE
20759 PORTS_MODULE_ID index ,
20760 PORTS_CHANNEL channel ,
20761 PORTS_BIT_POS bitPos ) ;
20800 PORTS_MODULE_ID index ,
20801 PORTS_CHANNEL channel ,
20802 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20835 PORTS_CHANGE_NOTICE_METHOD
20837 PORTS_MODULE_ID index ,
20838 PORTS_CHANNEL channel ) ;
20886 PORTS_MODULE_ID index ,
20887 PORTS_CHANNEL channel ,
20937 PORTS_MODULE_ID index ,
20938 PORTS_CHANNEL channel ,
20986 PORTS_MODULE_ID index ,
20987 PORTS_CHANNEL channel ,
20988 PORTS_BIT_POS bitPos ,
20989 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21032 PORTS_MODULE_ID index ,
21033 PORTS_CHANNEL channel ,
21034 PORTS_BIT_POS bitPos ) ;
21065 PORTS_MODULE_ID index ) ;
21089 PORTS_MODULE_ID index ) ;
21113 PORTS_MODULE_ID index ) ;
21137 PORTS_MODULE_ID index ) ;
21162 PORTS_MODULE_ID index ) ;
21187 PORTS_MODULE_ID index ) ;
21218 PORTS_MODULE_ID index ) ;
21246 PORTS_MODULE_ID index ) ;
21273 PORTS_MODULE_ID index ) ;
21298 PORTS_MODULE_ID index ) ;
21325 PORTS_MODULE_ID index ) ;
21350 PORTS_MODULE_ID index ) ;
21377 PORTS_MODULE_ID index ) ;
21402 PORTS_MODULE_ID index ) ;
21430 PORTS_MODULE_ID index ) ;
21458 PORTS_MODULE_ID index ) ;
21486 PORTS_MODULE_ID index ) ;
21512 PORTS_MODULE_ID index ) ;
21538 PORTS_MODULE_ID index ) ;
21564 PORTS_MODULE_ID index ) ;
21589 PORTS_MODULE_ID index ) ;
21615 PORTS_MODULE_ID index ) ;
21642 PORTS_MODULE_ID index ) ;
21667 PORTS_MODULE_ID index ) ;
21702 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21703 #define _PLIB_PORTS_COMPATIBILITY_H 21704 #include <stdint.h> 21705 #include <stddef.h> 21740 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21757 #include "system/int/sys_int.h" 21891 PORTS_MODULE_ID index ,
21892 PORTS_CHANNEL channel ) ;
21924 PORTS_MODULE_ID index ,
21925 PORTS_CHANNEL channel ,
21955 PORTS_MODULE_ID index ,
21956 PORTS_CHANNEL channel ) ;
21994 PORTS_MODULE_ID index ,
21995 PORTS_CHANNEL channel ,
22029 PORTS_MODULE_ID index ,
22030 PORTS_CHANNEL channel ,
22067 PORTS_MODULE_ID index ,
22069 PORTS_CHANNEL channel ,
22099 PORTS_MODULE_ID index ,
22100 PORTS_CHANNEL channel ) ;
22131 PORTS_MODULE_ID index ,
22132 PORTS_CHANNEL channel ,
22164 PORTS_MODULE_ID index ,
22165 PORTS_CHANNEL channel ,
22197 PORTS_MODULE_ID index ,
22198 PORTS_CHANNEL channel ,
22232 PORTS_MODULE_ID index ,
22233 PORTS_CHANNEL channel ) ;
22273 PORTS_MODULE_ID index ,
22274 PORTS_REMAP_INPUT_FUNCTION
function ,
22275 PORTS_REMAP_INPUT_PIN remapPin ) ;
22310 PORTS_MODULE_ID index ,
22311 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22312 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22345 PORTS_MODULE_ID index ) ;
22373 PORTS_MODULE_ID index ) ;
22407 PORTS_MODULE_ID index ,
22408 PORTS_CHANGE_NOTICE_PIN pinNum ,
22440 PORTS_MODULE_ID index ,
22441 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22470 PORTS_MODULE_ID index ) ;
22499 PORTS_MODULE_ID index ) ;
22530 PORTS_MODULE_ID index ,
22531 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22562 PORTS_MODULE_ID index ,
22563 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22602 PORTS_MODULE_ID index ,
22603 PORTS_ANALOG_PIN pin ,
22604 PORTS_PIN_MODE mode ) ;
22641 PORTS_MODULE_ID index ,
22642 PORTS_CHANNEL channel ,
22643 PORTS_BIT_POS bitPos ,
22678 PORTS_MODULE_ID index ,
22679 PORTS_CHANNEL channel ,
22680 PORTS_BIT_POS bitPos ) ;
22713 PORTS_MODULE_ID index ,
22714 PORTS_CHANNEL channel ,
22715 PORTS_BIT_POS bitPos ) ;
22748 PORTS_MODULE_ID index ,
22749 PORTS_CHANNEL channel ,
22750 PORTS_BIT_POS bitPos ) ;
22783 PORTS_MODULE_ID index ,
22784 PORTS_CHANNEL channel ,
22785 PORTS_BIT_POS bitPos ) ;
22818 PORTS_MODULE_ID index ,
22819 PORTS_CHANNEL channel ,
22820 PORTS_BIT_POS bitPos ) ;
22857 PORTS_MODULE_ID index ,
22859 PORTS_CHANNEL channel ,
22860 PORTS_BIT_POS bitPos ) ;
22893 PORTS_MODULE_ID index ,
22894 PORTS_CHANNEL channel ,
22895 PORTS_BIT_POS bitPos ) ;
22928 PORTS_MODULE_ID index ,
22929 PORTS_CHANNEL channel ,
22930 PORTS_BIT_POS bitPos ) ;
22963 PORTS_MODULE_ID index ,
22964 PORTS_CHANNEL channel ,
22965 PORTS_BIT_POS bitPos ) ;
22998 PORTS_MODULE_ID index ,
22999 PORTS_CHANNEL channel ,
23000 PORTS_BIT_POS bitPos ) ;
23033 PORTS_MODULE_ID index ,
23034 PORTS_CHANNEL channel ,
23035 PORTS_BIT_POS bitPos ) ;
23068 PORTS_MODULE_ID index ,
23069 PORTS_CHANNEL channel ,
23070 PORTS_BIT_POS bitPos ) ;
23103 PORTS_MODULE_ID index ,
23104 PORTS_CHANNEL channel ,
23105 PORTS_BIT_POS bitPos ,
23188 #ifndef _DRV_SPI_DEFINITIONS_H 23189 #define _DRV_SPI_DEFINITIONS_H 23195 #include <stdint.h> 23196 #include <stdbool.h> 23197 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23198 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23234 #ifndef _PLIB_SPI_H 23235 #define _PLIB_SPI_H 23269 #ifndef _PLIB_SPI_PROCESSOR_H 23270 #define _PLIB_SPI_PROCESSOR_H 23271 #error "Can't find header" 23316 SPI_MODULE_ID index ) ;
23346 SPI_MODULE_ID index ) ;
23378 SPI_MODULE_ID index ) ;
23410 SPI_MODULE_ID index ) ;
23444 SPI_MODULE_ID index ) ;
23474 SPI_MODULE_ID index ) ;
23511 SPI_MODULE_ID index ) ;
23550 SPI_MODULE_ID index ) ;
23580 SPI_MODULE_ID index ,
23611 SPI_MODULE_ID index ,
23645 SPI_MODULE_ID index ,
23646 SPI_COMMUNICATION_WIDTH width ) ;
23681 SPI_MODULE_ID index ,
23682 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23714 SPI_MODULE_ID index ,
23715 SPI_INPUT_SAMPLING_PHASE phase ) ;
23747 SPI_MODULE_ID index ,
23748 SPI_OUTPUT_DATA_PHASE phase ) ;
23779 SPI_MODULE_ID index ,
23780 SPI_CLOCK_POLARITY polarity ) ;
23810 SPI_MODULE_ID index ) ;
23840 SPI_MODULE_ID index ) ;
23878 SPI_MODULE_ID index ,
23879 uint32_t clockFrequency ,
23880 uint32_t baudRate ) ;
23911 SPI_MODULE_ID index ) ;
23943 SPI_MODULE_ID index ) ;
23976 SPI_MODULE_ID index ) ;
24009 SPI_MODULE_ID index ) ;
24041 SPI_MODULE_ID index ) ;
24071 SPI_MODULE_ID index ) ;
24102 SPI_MODULE_ID index ) ;
24133 SPI_MODULE_ID index ) ;
24164 SPI_MODULE_ID index ) ;
24196 SPI_MODULE_ID index ,
24197 SPI_FIFO_TYPE type ) ;
24229 SPI_MODULE_ID index ) ;
24261 SPI_MODULE_ID index ) ;
24295 SPI_MODULE_ID index ,
24296 SPI_FIFO_INTERRUPT mode ) ;
24326 SPI_MODULE_ID index ) ;
24356 SPI_MODULE_ID index ) ;
24388 SPI_MODULE_ID index ,
24389 SPI_FRAME_PULSE_DIRECTION direction ) ;
24422 SPI_MODULE_ID index ,
24423 SPI_FRAME_PULSE_POLARITY polarity ) ;
24456 SPI_MODULE_ID index ,
24457 SPI_FRAME_PULSE_EDGE edge ) ;
24490 SPI_MODULE_ID index ,
24491 SPI_FRAME_PULSE_WIDTH width ) ;
24525 SPI_MODULE_ID index ,
24526 SPI_FRAME_SYNC_PULSE pulse ) ;
24558 SPI_MODULE_ID index ) ;
24588 SPI_MODULE_ID index ) ;
24620 SPI_MODULE_ID index ) ;
24650 SPI_MODULE_ID index ) ;
24680 SPI_MODULE_ID index ) ;
24710 SPI_MODULE_ID index ) ;
24741 SPI_MODULE_ID index ,
24773 SPI_MODULE_ID index ,
24805 SPI_MODULE_ID index ,
24828 SPI_MODULE_ID index ) ;
24859 SPI_MODULE_ID index ,
24860 SPI_BAUD_RATE_CLOCK type ) ;
24892 SPI_MODULE_ID index ,
24893 SPI_ERROR_INTERRUPT error ) ;
24925 SPI_MODULE_ID index ,
24926 SPI_ERROR_INTERRUPT error ) ;
24957 SPI_MODULE_ID index ,
24958 SPI_AUDIO_ERROR error ) ;
24989 SPI_MODULE_ID index ,
24990 SPI_AUDIO_ERROR error ) ;
25020 SPI_MODULE_ID index ) ;
25050 SPI_MODULE_ID index ) ;
25082 SPI_MODULE_ID index ,
25083 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25115 SPI_MODULE_ID index ,
25116 SPI_AUDIO_PROTOCOL mode ) ;
25149 SPI_MODULE_ID index ) ;
25175 SPI_MODULE_ID index ) ;
25201 SPI_MODULE_ID index ) ;
25226 SPI_MODULE_ID index ) ;
25251 SPI_MODULE_ID index ) ;
25276 SPI_MODULE_ID index ) ;
25302 SPI_MODULE_ID index ) ;
25327 SPI_MODULE_ID index ) ;
25352 SPI_MODULE_ID index ) ;
25377 SPI_MODULE_ID index ) ;
25402 SPI_MODULE_ID index ) ;
25427 SPI_MODULE_ID index ) ;
25453 SPI_MODULE_ID index ) ;
25478 SPI_MODULE_ID index ) ;
25503 SPI_MODULE_ID index ) ;
25528 SPI_MODULE_ID index ) ;
25554 SPI_MODULE_ID index ) ;
25580 SPI_MODULE_ID index ) ;
25606 SPI_MODULE_ID index ) ;
25630 SPI_MODULE_ID index ) ;
25655 SPI_MODULE_ID index ) ;
25680 SPI_MODULE_ID index ) ;
25705 SPI_MODULE_ID index ) ;
25731 SPI_MODULE_ID index ) ;
25756 SPI_MODULE_ID index ) ;
25781 SPI_MODULE_ID index ) ;
25806 SPI_MODULE_ID index ) ;
25831 SPI_MODULE_ID index ) ;
25856 SPI_MODULE_ID index ) ;
25882 SPI_MODULE_ID index ) ;
25909 SPI_MODULE_ID index ) ;
25934 SPI_MODULE_ID index ) ;
25960 SPI_MODULE_ID index ) ;
25986 SPI_MODULE_ID index ) ;
26012 SPI_MODULE_ID index ) ;
26037 SPI_MODULE_ID index ) ;
26062 SPI_MODULE_ID index ) ;
26088 SPI_MODULE_ID index ) ;
26114 SPI_MODULE_ID index ) ;
26126 #include "system/common/sys_common.h" 26127 #include "system/common/sys_module.h" 26128 #include "system/int/sys_int.h" 26129 #include "system/clk/sys_clk.h" 26130 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26168 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26180 #define DRV_SPI_INDEX_0 0 26181 #define DRV_SPI_INDEX_1 1 26182 #define DRV_SPI_INDEX_2 2 26183 #define DRV_SPI_INDEX_3 3 26184 #define DRV_SPI_INDEX_4 4 26185 #define DRV_SPI_INDEX_5 5 26197 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26446 SPI_MODULE_ID
spiId ;
26479 CLK_BUSES_PERIPHERAL
spiClk ;
26639 const SYS_MODULE_INDEX index ,
26640 const SYS_MODULE_INIT *
const init ) ;
26682 SYS_MODULE_OBJ
object ) ;
26731 SYS_MODULE_OBJ
object ) ;
26772 SYS_MODULE_OBJ
object ) ;
26837 const SYS_MODULE_INDEX drvIndex ,
27432 #include "driver/usb/usbhs/drv_usbhs.h" 27433 #include "usb/usb_device.h" 27461 #include <stdint.h> 27481 uint8_t RevNumber ;
27568 SYS_MODULE_OBJ sysTmr ;
27569 SYS_MODULE_OBJ drvTmr0 ;
27570 SYS_MODULE_OBJ drvTmr1 ;
27571 SYS_MODULE_OBJ drvTmr2 ;
27572 SYS_MODULE_OBJ drvTmr3 ;
27573 SYS_MODULE_OBJ drvTmr4 ;
27574 SYS_MODULE_OBJ drvUsart0 ;
27575 SYS_MODULE_OBJ drvPMP0 ;
27577 SYS_MODULE_OBJ spiObjectIdx0 ;
27579 SYS_MODULE_OBJ spiObjectIdx1 ;
27581 SYS_MODULE_OBJ spiObjectIdx2 ;
27582 SYS_MODULE_OBJ drvUSBObject ;
27583 SYS_MODULE_OBJ usbDevObject0 ;
27643 bool write_complete ;
27647 uint8_t bytes_received ;
27770 #include <stdbool.h> 27771 #include <stdint.h> 27777 #define FIFO_RX_SIZE 7 27778 #define FIFO_TX_SIZE 7 27780 #define FIFO_ADD_OK 0 27781 #define FIFO_FULL 1 27783 #define FIFO_EMPTY 2U 27794 uint8_t * ptr_buffer ;
27799 uint8_t num_records ;
27800 uint8_t put_error ;
27801 uint8_t get_error ;
27842 uint8_t * ptrBuffer ,
27843 uint16_t Length ) ;
27930 TFifo * ptrFifo ) ;
27955 TFifo * ptrFifo ) ;
27982 #ifndef COMMMODULE_H 27983 #define COMMMODULE_H 27989 #include "../system_definitions.h" 28130 #include <stdbool.h> 28131 #include <stdint.h> 28172 uint8_t command [ 7 ] ;
28173 bool process_complete_flag ;
28174 bool b_command_complete_flag ;
28175 bool sw_status_bit_check ;
28421 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
28555 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 20)));
28599 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 25)));
28655 #define qqqbranches 99 28656 #define QQQMAXMCDCSIZE 2 28660 #define ldra_sscanf 28676 #undef qqnull_params 28677 #define qqnull_params void 28679 #define qqzzidfield 1 28685 #define QQQFIXEDSIZE 28705 qqcptr = qqscan_str;
28707 while (qqcptr[0] ==
' ')
28713 if (qqcptr[0] ==
'-')
28719 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
28721 qqvalue = 10 * qqvalue;
28722 qqvalue = qqvalue + (qqcptr[0] -
'0');
28725 qqvalue = qqisign * qqvalue;
28751 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
28752 ldra_port_write (&ldra_buffer[0]);
28760 ldra_port_write(s);
28768 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
28769 ldra_port_write (&ldra_buffer[0]);
28777 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
28778 ldra_port_write (&ldra_buffer[0]);
28786 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
28787 ldra_port_write (&ldra_buffer[0]);
28906 static int branches_printed = 0;
28910 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
28911 ldra_port_write (&ldra_buffer[0]);
28912 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
28913 ldra_port_write (&ldra_buffer[0]);
28915 branches_printed += 8;
28935 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 28936 #define LASTELEMENT 28937 #include "UART_71zbelem.def" static void DRV_TMR2_DeInitialize(void)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
void DRV_TMR1_StopInIdleEnable(void)
void DRV_TMR_Stop(DRV_HANDLE handle)
SPI_BAUD_RATE_CLOCK baudClockSource
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
SYS_DMA_CHANNEL_CHAIN_PRIO
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
static void DRV_TMR3_Tasks(void)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void Fifo_Init(TFifo *ptrFifo, uint8_t *ptrBuffer, uint16_t Length)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
bool DRV_TMR_Start(DRV_HANDLE handle)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_TMR3_StopInIdleEnable(void)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
bool DRV_TMR0_Start(void)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
void DRV_USART0_Deinitialize(void)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
uint32_t DRV_TMR3_PeriodValueGet(void)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT
void DRV_TMR3_CounterClear(void)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
static void Execute_Protocol_A(void)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
uint32_t SYS_DMA_ChannelCRCGet(void)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
void DRV_USART0_Close(void)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
uint32_t DRV_TMR0_PeriodValueGet(void)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
void DRV_TMR4_CounterValueSet(uint32_t value)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
static int UART_71zqzqzq(int qqqi)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
static int UART_71zscanf(char *qqscan_str)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint8_t jobQueueReserveSize
void DRV_TMR2_CounterClear(void)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
static int UART_71zqqzqz(qqnull_params)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
SYS_MODULE_INIT moduleInit
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
static int qqqqbmselwidth
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_ADC_DeInitialize(void)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t Fifo_Put(TFifo *ptrFifo, uint8_t Data)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void DRV_PMP0_Write(uint8_t data)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR3_Open(void)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
static int qqqisinitialised
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
static SYS_STATUS DRV_TMR2_Status(void)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR0_CounterValueGet(void)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
static void Execute_Auto_Protocol_A(void)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR0_DeInitialize(void)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
INT_SOURCE txInterruptSource
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
static void DRV_TMR1_Tasks(void)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint32_t DRV_TMR1_PeriodValueGet(void)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
void DRV_TMR1_CounterClear(void)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR3_Close(void)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
void DRV_TMR1_Initialize(void)
SPI_FRAME_PULSE_WIDTH framePulseWidth
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
static UART_STATES U_STATES
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
static void DRV_TMR4_Open(void)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
void DRV_TMR0_Initialize(void)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
bool DRV_SPIn_TransmitterBufferIsFull(void)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_TMR4_CounterValueGet(void)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
bool DRV_TMR1_Start(void)
static int UART_71zqendz(int qqqi)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
static void DRV_TMR2_Close(void)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
void DRV_USART_Close(const DRV_HANDLE handle)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
void DRV_ADC_Initialize(void)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
static void Execute_System(void)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_TMR3_Start(void)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_SPI_BUFFER_TYPE bufferType
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
bool DRV_SPIn_ReceiverBufferIsFull(void)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR2_StopInIdleDisable(void)
void DRV_TMR4_PeriodValueSet(uint32_t value)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
void(* ldra_void_function)()
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
static int qqqstructzzopen
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
void DRV_TMR0_CounterClear(void)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
void DRV_USART0_TasksTransmit(void)
struct _DRV_SPI_INIT DRV_SPI_INIT
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
static SYS_STATUS DRV_TMR1_Status(void)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void qqqtotalupload(void)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
static void qqqqinitialise(int ii)
void DRV_TMR0_PeriodValueSet(uint32_t value)
SPI_FRAME_PULSE_EDGE framePulseEdge
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void DRV_USART0_WriteByte(const uint8_t byte)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
uint8_t Fifo_Get(TFifo *ptrFifo)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
uint16_t DRV_IC0_Capture16BitDataRead(void)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR3_CounterValueSet(uint32_t value)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
static void DRV_TMR3_DeInitialize(void)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
static void ReadUART(void)
static SYS_STATUS DRV_TMR3_Status(void)
void DRV_TMR2_StopInIdleEnable(void)
static void WriteUART(void)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
uint32_t DRV_IC0_Capture32BitDataRead(void)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
uintptr_t DRV_USART_BUFFER_HANDLE
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR2_Tasks(void)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
static void DRV_TMR1_Close(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void PLIB_USART_Enable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
SYS_STATUS DRV_USART0_Status(void)
void SYS_DMA_Suspend(void)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
CLK_BUSES_PERIPHERAL spiClk
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
bool SYS_DMA_IsBusy(void)
DRV_USART_LINE_CONTROL_SET_RESULT
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
void SYS_PORTS_Initialize()
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static unsigned char qqqzzglobflag
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
SPI_COMMUNICATION_WIDTH commWidth
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void DRV_TMR2_PeriodValueSet(uint32_t value)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
static void qqqbitmapreset(qqnull_params)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
static SYS_STATUS DRV_TMR4_Status(void)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
#define DRV_IC_Close(handle)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
static SYS_STATUS DRV_TMR0_Status(void)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void DRV_TMR1_DeInitialize(void)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
DRV_USART_BAUD_SET_RESULT
static void DRV_TMR2_Open(void)
static void DRV_TMR0_Close(void)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
bool DRV_IC0_BufferIsEmpty(void)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
static void qqoutput(FILEPOINT char *s, int i)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR3_PeriodValueSet(uint32_t value)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
void DRV_TMR0_StopInIdleEnable(void)
static void DRV_TMR1_Open(void)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR2_CounterValueSet(uint32_t value)
uint32_t DRV_TMR2_CounterValueGet(void)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
void DRV_TMR1_PeriodValueSet(uint32_t value)
SYS_ERROR_LEVEL gblErrLvl
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
void DRV_TMR1_CounterValueSet(uint32_t value)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
bool DRV_USART0_TransmitBufferIsFull(void)
uint32_t DRV_TMR3_CounterValueGet(void)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
void PLIB_USART_Disable(USART_MODULE_ID index)
bool DRV_TMR4_Start(void)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
void DRV_IC0_Initialize(void)
void DRV_PMP0_ModeConfig(void)
void SYS_DEBUG_Message(const char *message)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
uintptr_t DRV_SPI_BUFFER_HANDLE
void DRV_TMR3_Initialize(void)
static void DRV_TMR4_Tasks(void)
uint32_t DRV_TMR2_PeriodValueGet(void)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
SPI_AUDIO_PROTOCOL audioProtocolMode
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint8_t DRV_PMP0_Read(void)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
void DRV_ADC0_Close(void)
DRV_SPI_CLOCK_MODE clockMode
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void SYS_DMA_Resume(void)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR4_Close(void)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
void DRV_TMR1_StopInIdleDisable(void)
SYS_DMA_CHANNEL_IGNORE_MATCH
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
uint8_t DRV_USART0_ReadByte(void)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
void DRV_TMR_Close(DRV_HANDLE handle)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void qqoutput0(FILEPOINT char *s)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
void DRV_TMR0_StopInIdleDisable(void)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
void DRV_TMR4_StopInIdleEnable(void)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
void DRV_IC_Stop(DRV_HANDLE handle)
void DRV_TMR4_Initialize(void)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
void DRV_USART0_TasksReceive(void)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
INT_SOURCE rxInterruptSource
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_TMR2_Start(void)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
static void DRV_TMR0_Open(void)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
static void DRV_TMR4_DeInitialize(void)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uintptr_t DRV_SPI_BUFFER_HANDLE
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
uintptr_t DRV_USART_BUFFER_HANDLE
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
INT_SOURCE errInterruptSource
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
ldra_void_function qqqaccumreset[QQQnumfil]
void APP_Initialize(void)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
void DRV_TMR4_CounterClear(void)
void DRV_TMR2_Initialize(void)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void DRV_TMR4_StopInIdleDisable(void)
void DRV_ADC1_Close(void)
static void qqqupload(qqnull_params)
uint32_t DRV_TMR1_CounterValueGet(void)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR3_StopInIdleDisable(void)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
void DRV_PMP0_Initialize(void)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
#define DRV_IC_Open(drvIndex, intent)
uint32_t DRV_TMR4_PeriodValueGet(void)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
void DRV_USART0_TasksError(void)
static void qqoutput2(FILEPOINT char *s, int i, int j)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
DRV_SPI_TASK_MODE taskMode
uint8_t Fifo_Length(TFifo *ptrFifo)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
bool Valid_Command(uchar8_t msg)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
static void DRV_TMR0_Tasks(void)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void Execute_Protocol_B(void)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
bool GetDepthStatus(void)
ldra_void_function qqqaccumupload[QQQnumfil]
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
SPI_FRAME_SYNC_PULSE frameSyncPulse
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DEBUG_Print(const char *format,...)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void DRV_TMR0_CounterValueSet(uint32_t value)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
static struct bitmapstruct_t bitmapstruct
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
static void ValidateComm(void)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)